
9/21/2011
30
Steps To Reduce Power
Smaller/Efficient Designs
Better Algorithm Design
Power Optimization
– Reduce Clock Frequency
– Control Subsystem Execution (enabled/triggered subsystems)
– Low Power Design Libraries/FPGA Devices
64
Multi-rate Models to Reduce Clock Frequency
Power Optimization
Cycle accurate simulation and implementation
Multi
le or sin
le clock im
lementation
65
clk
clk_enable
enb_1_2_1
enb_1_2_0
clk_enable
Timing Controller
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