MATLAB SIMULINK HDL CODER 1 Manuale Utente Pagina 30

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9/21/2011
30
Steps To Reduce Power
Smaller/Efficient Designs
Better Algorithm Design
Power Optimization
Smaller/Efficient
Designs
Reduce Clock Frequency
Control Subsystem Execution (enabled/triggered subsystems)
Low Power Design Libraries/FPGA Devices
64
Multi-rate Models to Reduce Clock Frequency
Power Optimization
Cycle accurate simulation and implementation
Multi
p
le or sin
g
le clock im
p
lementation
pg p
65
clk
clk_enable
enb_1_2_1
enb_1_2_0
clk_enable
Timing Controller
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