MATLAB SIMULINK HDL CODER 1 Manuale Utente Pagina 18
- Pagina / 46
- Indice
- SEGNALIBRI
- 9/21/2011 1
- Introducing The Speakers 2
- MathWorks and Xilinx Goals 2
- MathWorks at a Glance 3
- MathWorks Today 3
- Key Industries 4
- Who is Who??? 4
- (A Brief Example) 5
- Why do we use FPGAs? 7
- Why Model-Based Design? 12
- Flexible Design Environment 15
- Fixed Point Analysis 16
- Automatic HDL Code Generation 16
- Integrating Legacy HDL Code 18
- Things to remember … 19
- IIR Low Pass Filter 21
- Hardware Design Challenges: 22
- Demo: HDL Workflow Advisor 22
- Identifying the critical path 24
- Balancing pipeline registers 25
- Distributed Pipelining 26
- Better Algorithm Design 30
- Control Subsystem Execution 31
- Modules can be tri 31
- HDL Verification 34
- Verification Challenges: 35
- Digital Down Converter 36
- Integrated HDL Verification 36
- HDL Simulator 38
- Challenges: 40
- Summary: Verification 41
- Example MathWorks Services 45
- Were Your Expectations Met? 46
- Next Steps … 46
- Questions? 46
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