MATLAB SIMULINK HDL CODER - RELEASE NOTES Guida Utente Pagina 78
- Pagina / 79
- Indice
- SEGNALIBRI
- Generator for 1
- Table of Contents 3
- Introduction 7
- The Xilinx DSP Block Set 8
- FIR Filter Generation 9
- Support for MATLAB 10
- System Resource Estimation 11
- Hardware Co-Simulation 12
- System Integration Platform 13
- Chapter 1: Introduction 14
- Installation 15
- Windows Installations 16
- Post Installation Tasks 17
- ModelSim SE 19
- Setting the Size 19
- Setting the Number of Entries 20
- Release Information 21
- Getting Started 23
- ® Simulator 24
- The Xilinx DSP Blockset 25
- Defining the FPGA Boundary 26
- Creating the DSP Design 28
- Generating the HDL Code 29
- Chapter 4: Getting Started 30
- DSP blockset 30
- Lesson 1 Summary 32
- Lab Exercise: Using Simulink 32
- Fixed-Point Numeric Precision 33
- Overflow and Round Modes 35
- Bit-Level Operations 36
- The Reinterpret Block 37
- The Convert Block 38
- The Concat Block 39
- Slice Block 40
- The BitBasher Block 41
- Lesson 2 Summary 42
- Lab Exercise: Signal Routing 42
- Lesson 3 - System Control 43
- The MCode Block 44
- State Machine Example 46
- The Expression Block 47
- Reset and Enable Ports 48
- Bursty Data 49
- Lesson 3 Summary 50
- Lab Exercise: System Control 50
- Lesson 4 - Multi-Rate Systems 51
- Up and Down Sampling Blocks 52
- Debugging Tools 55
- Sample Period “Rules” 56
- Lesson 5 - Using Memories 58
- Initializing RAMs and ROMs 59
- System Generator RAM Blocks 60
- System Generator ROM Blocks 61
- The Delay Block 62
- The FIFO Block 63
- Shared Memory Block 64
- Lab Exercise: Using Memories 65
- Lesson 6 - Designing Filters 66
- The Virtex DSP48 Math Slice 67
- FIR Compiler Block 68
- Using FDA Tool Coefficients 70
- Virtex®-5 architecture 71
- AXI4 Conversion Examples 72
- Black Box Examples 72
- ChipScope Examples 73
- DSP Examples 73
- M-Code Examples 74
- Processor Examples 75
- Shared Memory Examples 75
- Miscellaneous Examples 76
- System Generator Demos 77
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