MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS Manuale Utente Scaricare il pdf (Pagina 31)

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30 DSP Selection Guide

ADSP-2100 Architecture

Providing over 15 Years of Code-Compatible DSP Excellence

The ADSP-2100 family architecture is built

around a common instruction set architecture

(ISA) which is optimized for signal processing.

All instructions are executed in a single clock

cycle, including multi-function instructions. The

architecture also features a high level algebraic

programming syntax.

In addition, ADSP-21xx processors operate on

24-bit instructions and 16-bit data. The wider

instruction word allows the device to use a more

complex and robust instruction set than a 16-bit

opcode. The 16-bit data word provides wide

dynamic range, while the narrower bus width

(16-bit as opposed to 32- or 64-bit wide) reduces

power consumption.

Processors are available with up to 2.4 Mbits of

SRAM around the DSP core to increase code

execution and overall system performance. All

ADSP-21xx processors integrate a program-

mable DMA controller to support maximum I/O

throughput and processor efficiency. The

ADSP-218x supports up to 4 Mbytes of external

memory while the ADSP-219x architecture

increases its address bus to 24-bits to support a

total of 16M words of external memory. The

ADSP-219x also balances a high performance

processor core with high performance buses

(PM, DM, DMA). It also provides two 40-bit

accumulators and a 40-bit shifter, which help

minimize data overflow during complex opera-

tions.

Addressing modes

ADSP-21xx processors also support immediate,

rect addressing modes. The ADSP-219x adds

fy, and direct- and indirect-offset addressing

modes. Each address generator supports as many

as four circular buffers, each with three registers.

The ADSP-219x supports as many as 16 circular

buffers using a DAG shadow register set and a

set of base registers for additional circular-

buffering flexibility.

24PM Addr

24DM Addr

24PM Data

16DM Data

Inst

Sequencer

ProgramSequencer

Cache

DAG1 DAG2

PM DM

JTAG and

Emulation

ALU MAC Shift

Data Registers

Peripheral and

DMA Interface

ADSP-219x Core Enhanced Features

Compiler-efficient Data Register File

Up to 16M words of address range

Unified memory space

Instruction Cache

DSP Processor Core

Internal Memory

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MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS Manuale Utente Pagina 31

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